本書系統(tǒng)介紹用于電子、光電子和MEMS器件的2.5D、3D以及3D IC集成和封裝技術(shù)的前沿進(jìn)展和演變趨勢，討論SD Ic集成和封裝關(guān)鍵技術(shù)的主要工藝問題和解訣方案。主要內(nèi)容包括半導(dǎo)體工業(yè)中的集成電路發(fā)展，摩爾定律的起源和演變歷史，三維集成和封裝的優(yōu)勢和挑戰(zhàn)，TSV制程與模型、晶圓減薄與薄晶圓在封裝組裝過程中的拿持晶圓鍵合技術(shù)、三維堆疊的微凸點制作與組裝技術(shù)、3D硅集成、2.5D/3D IC和無源轉(zhuǎn)接板的3D IC集成、三維器件集成的熱管理技術(shù)、封裝基板技術(shù)，以及存儲器、LED、MEMS、CIS 3D IC集成等關(guān)鍵技術(shù)問題，最后討論PoP、Fanin WLP、eVLP、ePLP等技術(shù)。
Preface
1 3D Integration for Semiconductor IC Packaging
1.1 Introduction
1.2 3D Integration
1.3 3D IC Packaging
1.4 3D Si Integration
1.5 3D IC Integration
1.5.1 Hybrid Memory Cube
1.5.2 Wide I/O DRAM and Wide I/O 2
1.5.3 High Bandwidth Memory
1.5.4 Wide I/O Memory (or Logic-on-Logic)
1.5.5 Passive Interposer (2.5D IC Integration)
1.6 Supply Chains before the TSV Era
1.6.1 FEOL (Front-End-of-Line)
1.6.2 BEOL (Back-End-of-Line)
1.6.3 OSAT (Outsourced Semiconductor Assembly and Test)
1.7 Supply Chains for the TSV Era-Who Makes the TSV
1.7.1 TSVs Fabricated by the Via-First Process
1.7.2 TSVs Fabricated by the Via-Middle Process
1.7.3 TSVs Fabricated by the Via-Last (from the Front Side) Process
1.7.4 TSVs Fabricated by the Via-Last (from the Back Side) Process
1.7.5 How About the Passive TSV Interposers
1.7.6 Who Wants to Fabricate the TSV for Passive Interposers
1.7.7 Summary and Recommendations
1.8 Supply Chains for the TSV Era-Who Does the MEOL, Assembly, and Test
1.8.1 Wide I/O Memory (Face-to-Back) by TSV Via-Middle Fabrication Process
1.8.2 Wide I/O Memory (Face-to-Face) by TSV Via-Middle Fabrication Process
1.8.3 Wide I/O DRAM by TSV Via-Middle Fabrication Process
1.8.4 2.5D IC Integration with TSV/RDL Passive Interposers
1.8.5 Summary and Recommendations
1.9 CMOS Images Sensors with TSVs
1.9.1 Toshiba's DynastronTM
1.9.2 STMicroelectronics' VGA CIS Camera Module
1.9.3 Samsung's S5K4E5YX BSI CIS
1.9.4 Toshiba's HEW4 BSI TCM5103PL
1.9.5 Nemotek's CIS
1.9.6 SONY's ISX014 Stacked Camera Sensor
1.10 MEMS with TSVs
1.10.1 STMicroelectronics’ MEMS Inertial Sensors
1.10.2 Discera's MEME Resonator
1.10.3 Avago's FBAR MEMS Filter
1.11 References
2 Through-Silicon Vias Modeling and Testing
2.1 Introduction
2.2 Electrical Modeling of TSVs
2.2.1 Analytic Model and Equations for a Generic TSV Structure
2.2.2 Verification of the Proposed TSV Model in Frequency Domain
2.2.3 Verification of the Proposed TSV Model in Time Domain
2.2.4 TSV Electrical Design Guideline
2.2.5 Summary and Recommendations
2.3 Thermal Modeling of TSVs
2.3.1 Cu-Filled TSV Equivalent Thermal Conductivity Extraction
2.3.2 Thermal Behavior of a TSV Cell
2.3.3 Cu-Filled TSV Equivalent Thermal Conductivity Equations
2.3.4 Verification of the TSV Equivalent Thermal Conductivity Equations
2.3.5 Summary and Recommendations
2.4 Mechanical Modeling and Testing of TSVs
2.4.1 TEM between the Cu-Filled TSV and Its Surrounding Si
2.4.2 Experimental Results on Cu Pumping during Manufacturing
2.4.3 Cu Pumping under Thermal Shock Cycling
2.4.4 Keep-Out-Zone of Cu-Filled TSVs
2.4.5 Summary and Recommendations
2.5 References
3 Stress Sensors for Thin-Wafer Handling and Strength Measurement
4 Package Substrate Technologies
5 Microbumps: Fabrication, Assembly, and Reliability
6 3D Si Integration
7 2.5D/3D IC Integration
8 3D IC Integration with Passive Interposer
9 Thermal Management of 2.5D/3D IC Integration
10 Embedded 3D Hybrid Integration
11 3D LED and IC Integration
12 3D MEMS and IC Integration
13 3D CMOS Image Sensor and IC Integration
14 3D IC Packaging
Index
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